Method for fabricating transistor gate structures and gate dielectrics thereof

ABSTRACT

Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No.10/185,326, filed on Jun. 28, 2002, entitled ANNEAL SEQUENCE FOR HIGH-KFILM PROPERTY OPTIMIZATION; U.S. patent application Ser. No. 10/232,124,filed on Aug. 30, 2002, entitled GATE STRUCTURE AND METHOD; and U.S.Pat. No. 6,544,906, filed Oct. 25, 2001, entitled ANNEALING OF HIGH-KDIELECTRIC MATERIALS, wherein the entirety of these applications andpatents are hereby incorporated by reference as if fully set forthherein.

FIELD OF INVENTION

The present invention relates generally to semiconductor devices andmore particularly to methods for fabricating and treating highdielectric constant gate dielectrics for MOS transistor gate structures.

BACKGROUND OF THE INVENTION

Field effect transistors (FETs) are widely used in the electronicsindustry for switching, amplification, filtering, and other tasksrelated to both analog and digital electrical signals. Most common amongthese are metal-oxide-semiconductor field-effect transistors (MOSFET orMOS), in which a gate is energized to create an electric field in anunderlying channel region of a semiconductor body, by which electronsare allowed to travel through the channel between a source region and adrain region of the semiconductor body. Complementary MOS (CMOS) deviceshave become widely used in the semiconductor industry, wherein bothn-channel and p-channel (NMOS and PMOS) transistors are used tofabricate logic and other circuitry.

The source and drain are typically formed by adding dopants to targetedregions of a semiconductor body on either side of the channel. A gatestructure is formed above the channel, having a gate dielectric formedover the channel and a gate electrode above the gate dielectric. Thegate dielectric is an insulator material, which prevents large currentsfrom flowing into the channel when a voltage is applied to the gateelectrode, while allowing such an applied gate voltage to set up anelectric field in the channel region in a controllable manner.Conventional MOS transistors typically include a gate dielectric formedby depositing or growing silicon dioxide (SiO₂) over a silicon wafersurface, with doped polysilicon formed over the SiO₂ to act as the gateelectrode.

Continuing trends in semiconductor device manufacturing includereduction in electrical device feature sizes (scaling), as well asimprovements in device performance in terms of device switching speedand power consumption. MOS transistor performance may be improved byreducing the distance between the source and the drain regions under thegate electrode of the device, known as the gate or channel length, andby reducing the thickness of the layer of gate oxide that is formed overthe semiconductor surface. However, there are electrical and physicallimitations on the extent to which thickness of SiO₂ gate dielectricscan be reduced. For example, very thin SiO₂ gate dielectrics are proneto large gate tunneling leakage currents resulting from direct tunnelingthrough the thin gate oxide. In addition, there are conventionallimitations on the ability to form such thin oxide films with uniformthickness. Furthermore, thin SiO₂ gate dielectric layers provide a poordiffusion barrier to dopants, for example, and may allow high borondopant penetration into the underlying channel region of the siliconduring fabrication of the source/drain regions.

Recent MOS transistor scaling efforts have accordingly focused on high-kdielectric materials having dielectric constants greater than that ofSiO₂ (e.g., greater than about 3.9), which can be formed in a thickerlayer than scaled SiO₂, and yet which produce equivalent field effectperformance. The relative electrical performance of such high-kdielectric materials is often expressed as equivalent oxide thickness(EOT), because the high-k material layer may be thicker, while stillproviding the equivalent electrical effect of a much thinner layer ofSiO₂. Since the dielectric constant “k” is higher than that of silicondioxide, a thicker high-k dielectric layer can be employed to mitigatetunneling leakage currents, while still achieving the equivalentelectrical performance of a thinner layer of thermally grown SiO₂,nitrided SiO₂, or SiON.

The performance and reliability of the resulting MOS transistors isdependent upon the quality of the high-k gate dielectric material,including the bulk high-k material and also the quality of the interfaceregion between the high-k gate dielectric material and the underlyingsilicon. Unlike SiO₂, which may be formed by thermal oxidation (growthprocess), high-k dielectrics are typically deposited over thesemiconductor substrate, using chemical vapor deposition (CVD), physicalvapor deposition (PVD), atomic layer deposition (ALD), molecular beamepitaxy (MBE), or other deposition processes. While the macroscopiccomposition (e.g., stoichiometry) of these materials may be controlledto a certain extent during such deposition processes, stoichiometriccomposition variations within the film may degrade device performance.

In addition, the above deposition techniques often create high-kdielectric films having point defects that affect transistorperformance. Such defects may include oxygen vacancies, and/or otherpoint defects affecting leakage through the gate dielectric.Furthermore, certain deposition processes (e.g., CVD, ALD, etc.) mayintroduce impurities (e.g. Cl, C, OH, H, etc.) into the deposited high-kdielectric film, which also degrade device performance. Moreover, thedeposited film may not be of optimal density, wherein sub parperformance may result. Accordingly, there is a need for improved gatedielectric fabrication techniques by which high quality gate dielectricsand interfaces can be achieved.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later.

The invention provides methods for treating deposited high-k gatedielectric films and gate fabrication techniques, by which improved gatedielectric materials may be realized. A deposited dielectric film orlayer is subjected to one or more non-oxidizing anneals to densify thematerial and one or more oxidizing anneals to mitigate material defects.In addition, the film is nitrided to inhibit dopant diffusion and tothermally stabilize the deposited material. The nitridation may be donefirst, or one or more of the anneals can be performed prior tonitridation to densify and/or heal defects resulting from the initialdeposition process. After nitridation, one or more anneals may beperformed to address any defects, impurities, etc. introduced during thenitridation, wherein the post-nitridation annealing may be performed athigh temperatures without crystallization, due to the presence ofnitrogen in the film.

One aspect of the invention combines a post-deposition nitridationprocess with two or more post-deposition anneal operations, where one isoxidizing and one is non-oxidizing. In accordance with this aspect, amethod is provided for treating a deposited high-k gate dielectric layerduring fabrication of a semiconductor device. The method comprisesnitriding a deposited high-k gate dielectric layer, performing a firstanneal in a non-oxidizing ambient, and performing a second anneal in anoxidizing ambient. In one implementation, the nitridation is done priorto both the anneal processes, with the non-oxidizing anneal being donelast (e.g., prior to depositing the gate electrode material). In anotherimplementation, the non-oxidizing anneal is done prior to nitridation.Either implementation may be used in conjunction withnitrogen-containing high-k materials or with materials initiallydeposited with no nitrogen content, wherein the nitridation step mayimprove thermal stability of the deposited material in either case.

Another aspect of the invention provides a post-deposition nitridationprocess, along with one or more pre-nitridation anneal processes and oneor more post-nitridation anneal processes to treat the high-k material.In one example, the pre-nitridation anneals include a first anneal at amoderate temperature in a non-oxidizing ambient that operates to densifythe deposited high-k material, wherein the temperature of the firstanneal may be adjusted to avoid crystallizing the material, particularlyimportant for deposited films initially having no nitrogen content. Asecond pre-nitridation anneal is then performed at moderate temperaturesin an oxidizing ambient to reduce or eliminate defects and impurities inthe high-k dielectric before nitridation. The post nitridation annealingin this example includes a third anneal process performed at a hightemperature in a non-oxidizing ambient to densify the material, followedby a fourth anneal at a somewhat lower temperature in an oxidizingambient to control point defects.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified flow diagram illustrating an exemplary method offabricating transistor gate structures in accordance with the presentinvention;

FIG. 2 is a flow diagram illustrating another exemplary method offabricating transistor gate structures in accordance with the invention;

FIGS. 3A-3I are partial side elevation views in section illustrating asemiconductor device at various stages of fabrication processing whereina high-k gate dielectric is formed and treated in accordance with themethod of FIG. 2; and

FIG. 4 is a flow diagram illustrating another exemplary method offabricating transistor gate structures in which a deposited high-k gatedielectric material layer undergoes a high temperature non-oxidizinganneal prior to nitridation or undergoes nitridation prior to a hightemperature inert non-oxidizing anneal in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now bedescribed with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the devices and structures illustrated in the figures are notnecessarily drawn to scale.

The invention relates to post-deposition treatment of deposited high-kgate dielectric films to densify the material, heal defects, and tothermally stabilize the material through multiple anneal processes and anitridation process. The methods of the invention can be employedfollowing high-k deposition and before formation of gate electrodematerials over the high-k, to improve the high-k material quality (e.g.,reduce point and other defects, densify the material, remove impurities,etc.). The techniques of the invention may be employed in conjunctionwith any high-k dielectric materials having a dielectric constant “k”greater than that of SiO₂ (e.g., greater than about 3.9), and areindependent of the particular deposition process used to initially formthe high-k film. In addition, the invention may be employed in devicesfabricated using any semiconductor body (e.g., silicon substrates, SOIwafers, etc.), and may be used in transistors having any type of gateelectrode material(s) (e.g., polysilicon, metal gates, etc.).

Referring initially to FIG. 1, a gate fabrication method 10 ishereinafter illustrated and described in accordance with one or moreaspects of the present invention. Although the exemplary method 10 andother methods of the invention are illustrated and described below as aseries of acts or events, it will be appreciated that the presentinvention is not limited by the illustrated ordering of such acts orevents. For example, some acts may occur in different orders and/orconcurrently with other acts or events apart from those illustratedand/or described herein, in accordance with the invention. In addition,not all illustrated steps may be required to implement a methodology inaccordance with the present invention. Further, the methods according tothe present invention may be implemented in association with theformation and/or processing of structures illustrated and describedherein as well as in association with other structures and devices notillustrated.

Beginning at 12, the method 10 comprises depositing a high-k gatedielectric layer at 14. Any dielectric may be deposited at 14 having adielectric constant higher than that of SiO₂, including but not limitedto binary metal oxides including aluminum oxide (Al₂O₃), zirconium oxide(ZrO₂), hafnium oxide (HfO₂), lanthanum oxide (La₂O₃), yttrium oxide(Y₂O₃), titanium oxide (TiO₂), as well as their silicates andaluminates; metal oxynitrides including aluminum oxynitride (AlON),zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanumoxynitride (LaON), yttrium oxynitride (YON), as well as their silicatesand aluminates such as ZrSiON, HfSiON, LaSiON, TaSiON, YSiON, ZrAlON,HfAlON, TaAlON, etc.; and perovskite-type oxides including a titanatesystem material such as barium titanate, strontium titanate, bariumstrontium titanate (BST), lead titanate, lead zirconate titanate, leadlanthanum zirconate titanate, barium lanthanum titanate, bariumzirconium titanate; a niobate or tantalate system material such as leadmagnesium niobate, lithium niobate, lithium tantalate, potassiumniobate, strontium aluminum tantalate and potassium tantalum niobate; atungsten-bronze system material such as barium strontium niobate, leadbarium niobate, barium titanium niobate; and Bi-layered perovskitesystem material such as strontium bismuth tantalate, bismuth titanateand others. Furthermore, any deposition process or processes may beemployed in depositing the high-k film at 14, including but not limitedto CVD, PVD, ALD, MBE, or others.

Following the high-k deposition at 14, a multi-step treatment isperformed at 16, including one or more pre-nitridation anneals at 18, anitridation process at 20, and one or more post-nitridation anneals at22. As illustrated and described further below with respect to FIGS. 2and 3A-3I, the multi-step treatment 16 may advantageously comprise firstand second pre-nitridation anneals at 18, wherein a first anneal isperformed at a moderate temperature in an inert non-oxidizing ambientfor densifying the deposited high-k material, as well as a secondpre-nitridation anneal at 18 that is performed in an oxidizing ambientfor curing defects and eliminating impurities. Moreover, thepost-nitridation annealing at 22 in the example below advantageouslyincludes a third anneal performed at a high temperature in anon-oxidizing ambient to densify the thermally stabilized high-kmaterial and a fourth anneal in an oxidizing ambient to reduce anyremaining defects and impurities.

At 24, a gate electrode material (e.g., polysilicon, metals, metalsilicides, metal oxides, metal nitrides, or stacks combinations thereof)is formed over the treated high-k dielectric, using any suitabledeposition process. The gate dielectric and gate electrode materiallayers are then patterned at 26 (e.g., using suitable etch masks andreactive ion etching (RIE) or other selective material removalprocesses) to create a patterned gate structure over a prospectivechannel region of the underlying semiconductor body, and the gatefabrication method 10 ends at 28. Thereafter, further processing stepsmay be undertaken to complete fabrication of a finished MOS transistor,for example, including implantation of source/drain regions of thesubstrate (e.g., as well as implantation of a polysilicon gate electrodematerial), silicidation to form contacts over the gate and thesource/drains, and metalization or interconnect processing (not shown).

Referring now to FIGS. 2 and 3A-3I, an exemplary implementation of theinvention is illustrated and described in the context of treating adeposited high-k dielectric prior to formation of a gate electrodematerial thereover. FIG. 2 illustrates a gate fabrication method 50 andFIGS. 3A-3I illustrate an exemplary semiconductor device 102 undergoinggate fabrication processing generally in accordance with the method 50.Beginning at 52 in FIG. 2, a high-k dielectric (e.g., such as thosedescribed above) is deposited or otherwise formed at 54 over or above asemiconductor body. In one example, HfSiO or HfSiON may be depositedover a silicon substrate at 54 via CVD, PVD, ALD, PECVD, PEALD, MBE, orother suitable deposition process.

In FIG. 3A, the exemplary device 102 is illustrated after shallow trenchisolation (STI) or field oxide (LOCOS) isolation structures 112 and oneor more wells 118 have been formed in a silicon wafer substrate 104. Apre-deposition cleaning operation 116 is performed in FIG. 3A. In FIG.3B, a CVD process 122 is used to deposit a HfSiO high-k dielectric layer120 at a deposition temperature below about 700 degrees C. It is notedin this example, that other high-k materials may be deposited at 54 inthe method 50, including those having nitrogen content (e.g., HfSiON,etc.). As noted above, the deposited high-k layer may includestoichiometric composition variations, defects that affect transistorperformance (e.g., oxygen vacancies, and/or other point defects that maylead to gate dielectric leakage and/or interface states). In thisregard, the deposition process at 54 may itself introduce impuritiesinto the deposited high-k dielectric film, which also degrade deviceperformance. For example, CVD or ALD deposited HfSiO may includeundesirable C, OH, H, Cl, or other impurities, wherein ALD deposition istypically at a lower temperature (e.g., about 300 degrees C.) and thecorresponding presence of C, OH, or Cl impurities is higher.

As discussed above, the optimization of the high-k dielectric filmproperties with respect to transistor performance is facilitated by filmdensification, nitrogen incorporation, and defect/impurity reductionthrough oxidation, wherein nitrogen incorporation may be preceded bydensification. In addition, defect/impurity reduction can be facilitatedby high temperature annealing, where nitrogen incorporation (e.g.,thermal stabilization) facilitates the use of higher annealingtemperatures without crystallizing the deposited high-k material. Lowtemperature oxidizing anneals avoid increases in the EOT of thematerial, but generally do not densify the material. At the same time,non-oxidizing high temperature anneals (e.g., Ar, He, or N₂ ambient)facilitate densification, but typically do not heal defects or adjustfor non-stoichiometry.

It is noted with respect to HfSiO and HfSiON that while initiallyincluding nitrogen in the high-k material as deposited facilitateshigher temperature annealing, HfSiO has been found to be easier todeposit at 54 than HfSiON. The same may be true of other non-nitrogencontaining deposited high-k materials. Moreover, the introduction offurther nitrogen into materials that initially contained nitrogen (e.g.,HfSiON as deposited) is believed to benefit the high-k film propertiesand the resulting device performance. In this regard, a post-depositionnitridation can be used to fine tune the nitrogen content and profilethroughout the depth of the high-k film, for example, with little or nonitrogen at the interface between the substrate and the high-k material.

Accordingly, to address these interrelationships between depositionprocessing, annealing, nitrogen incorporation, densification,defect/impurity reduction, etc., the exemplary method 50 includes anitridation at 70, as well as pre and post nitridation annealing at 60and 80, respectively, to reduce defects/impurities, densify the high-kmaterial, and incorporate nitrogen therein, without creating unwantedlow-k oxidation at the dielectric/substrate interface. In general,deposited materials that include nitrogen content (as deposited) may beannealed at somewhat higher temperatures at 60, wherein the pre andpost-nitridation anneal temperatures can be tailored to preventcrystallization of the high-k material. For example, deposited HfSiO hasbeen found to crystallize at about 900 degrees C., whereas HfSiON may bestable above about 1100 degrees C., depending on the composition (Hf toSi ratio and N to O ratio). The same general relationships are believedto be true for other high-k dielectrics, where nitrogen incorporation at54 increases the thermal stability allowing higher anneal temperaturesat 60, wherein such thermal stability considerations may be taken intoaccount in determining both the pre and post nitridation annealtemperatures at 60 and 80, respectively.

At 60, pre-nitridation annealing of the high-k material is performed toaddress densification, defects, and impurity issues that may have arisenduring the deposition at 54. A dual anneal sequence is employed at 60,including an inert anneal at 62 and an oxidizing anneal at 64. Suitablefirst and second anneal processes are described in U.S. patentapplication Ser. No. 10/185,326, assigned to the assignee of the presentinvention Texas Instruments Incorporated, the entirety of which ishereby incorporated by reference as if fully set forth herein. In theexemplary method 50, a first (pre-nitridation) anneal is performed at amoderate temperature at 62 in an inert non-oxidizing ambient, in orderto initially densify the deposited high-k material.

As illustrated in FIG. 3C, the device 102 undergoes a first annealprocess 124 to densify the high-k material 120. The first anneal 124occurs in a non-oxidizing ambient, for example, comprising Ar, He, or N₂at a relatively high or moderate temperature, preferably in the range of700° C. to 1100° C., for about 60 seconds in one example to densify thehigh-k gate dielectric 120. In the illustrated example of depositedHfSiO or HfSiON, the first anneal 124 (62 in FIG. 3) is performed at atemperature of about 1000 degrees C. or less (e.g., deposited HfSiON),preferably about 900 degrees C. or less (e.g., deposited HfSiO), such asabout 700 to 900 degrees C., in a non-oxidizing ambient comprising N₂,Ar, He, Ne, or other inert gas environment. In this example, the firstanneal at 62 operates to completely or partially densify the depositedhigh-k material wherein applying thermal energy allows the depositedatoms to slightly rearrange themselves into more stable positions,leaving fewer dangling bonds in a higher density material, withoutexcessive atomic rearrangement (e.g., without crystallization or phaseseparation). This, in turn, leads to fewer interface states and lowerdielectric leakage in the finished MOS transistor device 102.

Referring also to FIG. 3D, a second anneal is performed at 64 (annealprocess 126 in FIG. 3D), wherein an oxidizing ambient is used to healoxygen defects, and to eliminate or reduce carbon, hydrogen, chlorine,or other impurities. In one implementation, the second anneal at 64 isperformed at a temperature of about 1000 degrees C. or less, preferablyabout 700 degrees C. or less, at atmospheric pressure, preferably at apressure of about 1 Torr or less. This second anneal at 64, moreover,can be any form of relatively mild anneal in an oxidizing ambient toheal the film and interface defects incurred during the deposition at54. The oxidizing ambient may comprise, for example, O₂, N₂O, NO, ozone(O₃), UV O₂, or other suitable oxidizing ambient. The second anneal is apreferably performed at 64 at a lower temperature than the first annealat 62 (e.g., room temperature to 1000° C.), and may be a thermal anneal,with or without UV exposure, or a low temperature plasma process,wherein the process temperature, time and pressure may be selected so asnot to significantly increase the material EOT. In this regard, reducedpressure may be helpful in avoiding oxide growth (increased EOT),wherein reduced pressures may allow higher temperatures during thesecond anneal at 64.

For example, the second anneal may be performed at about 700 degrees C.in an O₂ ambient for about 60 sec at 1 Torr. The first and secondanneals at 60, as well as the nitridation 70 and/or the post-nitridationanneals at 80 may be separate processes or may be run as separate stepswithin one recipe. For example, depending on the anneal toolconfiguration, the dual pre-nitridation anneals at 60 may be performedin a single processing run with a multi-step annealing recipe. Thesecond anneal at 64 may alternatively comprise exposing the high-kdielectric layer to an oxidizing liquid solution, such as H₂O+H₂O₂,H₂O+O₃, H₂SO₄+H₂O₂+H₂O, H₂SO₄+H₂O, HNO₃+H₂O, HNO₃+H₂O₂+H₂O,HCl+H₂O₂+H₂O, or NH₄OH+H₂O₂+H₂O. Suitable liquid based oxidation surfacetreatments are set forth in U.S. patent application Ser. No. 10,232,124,filed on Aug. 30, 2002, assigned to the assignee of the presentinvention Texas Instruments Incorporated, the entirety of which ishereby incorporated by reference as if fully set forth herein.

In another alternative, the second anneal at 64 may comprise anoxidizing plasma process at 700 degrees or less (e.g., low temperatureoxidizing plasma process). In this case, the high-k material 120 isexposed to an oxygen plasma in an ambient including, for example, O₂with one or more of Ar, N₂O or NO, where the plasma provides energizedoxygen ions to the high-k material 120. In another possibleimplementation, the second anneal at 64 can be an ozone anneal, whereinthe process ambient includes O₃. In still another possibility, thesecond anneal can be a low temperature anneal (e.g., less than about 700degrees C.) with UV excitation, for example, wherein O₂ gas is energizedwith UV lamps to create atomic oxygen or O₃ that are provided to thehigh-k material 120.

Thereafter at 70, a plasma nitridation process is performed (process 128in FIG. 3E) to introduce nitrogen into the high-k material 120. Theplasma nitridation at 70 may be performed according to any suitableprocess parameters. One possible implementation is described in U.S.Pat. No. 6,136,654, issued Oct. 24, 2000 to Kraft et al., assigned tothe assignee of the present invention Texas Instruments Incorporated,the entirety of which is hereby incorporated by reference as if fullyset forth herein. In two possible implementations, the nitridation at 70may comprise a nitridation anneal, for example, in an NH₃ (e.g.,ammonia) ambient, or a plasma nitridation process. In the case of anammonia anneal, the nitridation at 70 may be performed in the sameprocess tool used for the pre and/or post anneals at 60 and 80.

The introduction of nitrogen can be used to block boron diffusion,thermally stabilize the film (e.g., raise the temperature ofcrystallization or phase separation), and to increase the dielectricconstant k. For example, for deposited HfSiO, the nitridation at 70creates HfSiON, which may be thermally stable above about 1100 degreesC. without crystallizing. Where the deposited film 120 already includesnitrogen, the nitridation 70 can be employed to tune the nitrogencontent/profile through the depth of the film. In order to avoid havingnitrogen at the interface, this nitridation step 70 can beadvantageously employed, for example, to introduce nitrogen primarilynear the top of the film 120. In the case of an ammonia (NH₃) anneal,the nitridation temperature may be about 1000 degrees C. or less. Plasmanitridation can alternatively be employed at 70, for example, includingperforming a decoupled-plasma-nitridation (DPN) or slot-plane-antenna(SPA) plasma nitridation process.

The inventors have appreciated that although the pre-nitridation annealsat 60 facilitate defect/impurity reduction and densification, somedefects/impurities may remain prior to the nitridation at 70.Furthermore, the nitridation at 70 itself may cause defects and/orintroduce impurities in the high-k dielectric 120. For instance, anammonia anneal at 70 can introduce H into the film 120, and may alsorenitride the substrate/high-k interface slightly. For a plasmanitridation at 70, the incoming nitrogen atoms are energized, and canknock oxygen out of the film 120, thereby creating new oxygen vacancies.Thus, the nitridation at 70 can recreate some of the defects that thepre-nitridation anneal 60 was meant to cure.

Accordingly, the method 50 further comprises one or morepost-nitridation anneals at 80. The post-nitridation anneals densify thematerial 120 through inert annealing at high temperature, and reoxidizethe material 120, wherein the reoxidation operates to heal defectscaused by the nitridation 70, eliminate hydrogen, potentially regrow theinterface to inhibit interface nitridation between the substrate 104 andthe high-k material 120, and to fix oxygen vacancies in the film 120. Inthe exemplary method 50, the post-nitridation anneals 80 include a hightemperature inert anneal at 82 to densify the film through slight atomicrearrangement without crystallization (third anneal process 130 in FIG.3F). This third anneal at 82 can be greater than about 1000 degrees C.in an inert ambient (e.g., comprising N₂, Ar, He, or Ne) for HfSiON orother high-k materials 120 due to the thermal stabilization afforded bythe nitridation at 70. Alternatively, any other suitable non-oxidizinganneal can be used at 82 that does not drastically change the filmcomposition profile (e.g., below the crystallization temperature).

At 84, a fourth anneal is performed (e.g., anneal process 132 in FIG.3G) at a mild temperature in an oxidizing ambient to fix the high-kmaterial composition and heal any remaining defects in the film 120. Thefourth anneal at 84 is preferably performed at a temperature of about1000 degrees C. or less, for example, about 700 degrees C. or less, andat a pressure of about 1 Torr or less in one example, or at atmosphericpressure in another example. As with the second anneal at 64, the fourthanneal may be any suitable oxidizing anneal process, such as exposingthe high-k dielectric layer to an oxidizing liquid solution (e.g.,H₂O+H₂O₂, H₂O+O₃, H₂SO₄+H₂O₂+H₂O, H₂SO₄+H₂O, HNO₃+H₂O, HNO₃+H₂O₂+H₂O,HCl+H₂O₂+H₂O, NH₄OH+H₂O₂+H₂O, etc.), an oxidizing plasma process, anozone anneal, a low temperature anneal with UV excitation, etc.

One, some or all of the anneals 60, 80, and the nitridation 70 may beperformed in a single process tool, for example, where the nitridationat 70 is an NH₃ anneal. Thereafter at 90, polysilicon gate electrodematerial is formed over the high-k dielectric 120 (e.g., polysiliconlayer 140 deposited via a deposition process 142 in FIG. 3H). At 92, thegate dielectric and gate electrode material layers are patterned tocreate a patterned gate structure over a prospective channel region ofthe underlying semiconductor body, and the gate fabrication method 50ends at 94. Further processing is then performed as illustrated in FIG.3I to implant source/drain regions 150 in the substrate 104 and to formsidewall spacers 160 along the lateral sides of the patterned gatestructure. Silicidation and metalization processing is thereafterperformed (not shown) to complete the fabrication of the device 102.

Referring now to FIG. 4, another aspect of the invention provides fordual high-k gate dielectric annealing (an oxidizing anneal and anon-oxidizing anneal) with material nitridation, wherein these threeprocesses may be performed in any order following the high-k depositionand before formation of an overlying gate electrode material. FIG. 4illustrates another method 200 for gate fabrication in accordance withthis aspect of the invention, beginning at 202, wherein the nitridationmay be performed prior to both anneals or between two anneals. A high-kgate dielectric material layer is deposited at 204, which may form anyhigh-k material such as those described above via any suitabledeposition process (e.g., CVD, PVD, ALD, MBE, etc.).

Thereafter, a three step treatment is performed at 210, including anitridation, an oxidizing anneal, and a non-oxidizing anneal. In oneimplementation, the method 200 proceeds to 212, where a first anneal isperformed in a non-oxidizing ambient at relatively high temperature. Thefirst anneal temperature is selected to densify the high-k materialwithout crystallization. Where the high-k material is initiallydeposited to include nitrogen, the first anneal temperature at 212 canbe higher than for material not initially deposited with nitrogen. Forexample, where HfSiO is deposited at 204, the first anneal at 212 ispreferably performed at a temperature of about 1000 degrees C. or less,more preferably at about 700 to 900 degrees C. in an inert ambient(e.g., N₂, Ar, He, or Ne) to reduce the likelihood of crystallization.For HfSiON deposited at 204, the non-oxidizing first anneal at 212 maybe performed at temperatures up to about 1100 degrees C.

At 214, the densified high-k material is nitrided using any suitablenitridation process, such as those described above. In one example, thenitridation at 214 comprises performing a nitridation anneal in anitrogen containing ambient, such as annealing at about 1000 degrees C.or less in an ammonia (NH₃) ambient. In another possible implementation,the nitridation at 212 is a plasma nitridation process (e.g., SPA, DPN,etc.).

Thereafter at 220, a second anneal is performed in an oxidizing ambientto heal oxygen defects, and to eliminate or reduce carbon, hydrogen,chlorine, or other impurities, including those associated with thedeposition process at 204 as well as those associated with thenitridation at 214. In one implementation, the second anneal at 220 isperformed at a temperature of about 1000 degrees C. or less, preferablyabout 700 degrees C. or less, at atmospheric pressure or a pressure ofabout 1 Torr or less. The oxidizing ambient may comprise, for example,O₂, N₂O, NO, ozone (O₃), UV O₂, or other suitable oxidizing ambient. Thesecond anneal at 220, moreover, may be a thermal anneal, with or withoutUV exposure, or a low temperature oxidizing plasma process, wherein theprocess temperature, time and pressure may be selected so as not tosignificantly increase the material EOT, such as the oxidizing annealsdescribed above. In another example, the second anneal at 220 maycomprise exposing the high-k dielectric layer to an oxidizing liquidsolution, such as H₂O+H₂O₂, H₂O+O₃, H₂SO₄+H₂O₂+H₂O, H₂SO₄+H₂O, HNO₃+H₂O,HNO₃+H₂O₂+H₂O, HCl+H₂O₂+H₂O, or NH₄OH+H₂O₂+H₂O, as described above.

Following the second anneal at 220, a gate electrode material (e.g.,polysilicon, etc.) is deposited at 222 over the treated high-kdielectric, using any suitable deposition process. At 224, the treatedhigh-k gate dielectric and gate electrode material layers are patternedto provide a patterned gate structure over the semiconductor body, andthe gate fabrication method 200 ends at 226. It is noted in thisexample, that the first anneal at 212 may need to be performed at amoderate temperature, particularly for non-nitrogen containing materialsdeposited at 204, since the nitridation (e.g., thermal stabilization) at214 is after the first anneal at 212. However, it is further noted thatthe nitridation 214 itself may be facilitated by densification of thehigh-k material through annealing at 212, which may improve tailoring ofthe nitrogen content and profile in the high-k material.

In another exemplary implementation of the method 200, thepost-deposition nitridation is performed prior to both of the annealprocesses. After the high-k deposition at 204, the method 200 proceedsto 216, where the high-k material is nitrided using any suitablenitridation process (e.g., a nitridation anneal in a nitrogen containingambient, SPA or DPN plasma nitridation, etc., as described above). Inthis example, the high-k material has not been densified at the time ofthe nitridation 216, but the nitridation at 216 may advantageously allowhigher temperature densification annealing by thermally stabilizing thematerial prior to the densification (e.g., non-oxidizing) anneal at 218.

After the nitridation at 216, the method proceeds to 218, where a firstanneal is performed in a non-oxidizing ambient to densify the material.The first anneal can be performed according to any of the non-oxidizinganneal examples set forth above, wherein the annealing temperature maybe relatively high because the high-k material has been thermallystabilized by the nitridation at 216. In this example, the incorporationof nitrogen at 216 may proceed at a higher rate in the non-densifiedmaterial than for the above case where the material is first densified(e.g., 212 and 214 in FIG. 4), which may be advantageous fornon-nitrogen containing deposited films. Thereafter, the method 200proceeds to the second (e.g., oxidizing) anneal 220, electrodedeposition 222 and patterning at 224 as described above, before themethod 200 ends at 226.

Although the invention has been illustrated and described with respectto one or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

1. A method for treating a deposited high-k gate dielectric layer duringfabrication of a semiconductor device, the method comprising: nitridinga deposited high-k gate dielectric layer prior to forming a gateelectrode; performing a first anneal of the deposited high-k dielectricin a non-oxidizing ambient prior to forming a gate electrode; andperforming a second anneal of the deposited high-k dielectric in anoxidizing ambient prior to forming a gate electrode.
 2. The method ofclaim 1, wherein the second anneal is performed after nitriding thehigh-k dielectric layer and after performing the first anneal. 3-13.(canceled)
 14. The method of claim 2, wherein the first anneal isperformed after nitriding the high-k dielectric layer.
 15. The method ofclaim 14, wherein the first anneal is performed at a temperature aboveabout 1000 degrees C.
 16. The method of claim 15, wherein thenon-oxidizing ambient of the first anneal comprises N2, Ar, He, or Ne.17. The method of claim 14, wherein the non-oxidizing ambient of thefirst anneal comprises N2, Ar, He, or Ne.
 18. The method of claim 14,wherein nitriding the deposited high-k gate dielectric layer comprisesperforming a nitridation anneal in a nitrogen containing ambient. 19.The method of claim 18, wherein the nitridation anneal is performed at atemperature of about 1000 degrees C. or less and wherein the nitrogencontaining ambient comprises NH₃.
 20. The method of claim 14, whereinnitriding the deposited high-k gate dielectric layer comprisesperforming a plasma nitridation process.
 21. The method of claim 14,wherein the second anneal is performed at a temperature of about 1000degrees C. or less. 22-67. (canceled)